Join us for a joint CMC/SoC Labs technical workshop focused on the latest initiatives that simplify System-on-Chip (SoC) design and fabrication.
This session will walk through the full SoC development lifecycle using nanoSoC, an Arm-based microcontroller SoC reference design, and demonstrate how silicon-proven Cadence workflows and a GlobalFoundries technology node—available through CMC—can help reduce design barriers and accelerate innovation.
You will see how re-usable IP, maintained tool environments, and workflow examples can make SoC design more accessible for both new and experienced developers. The workshop also highlights real accelerator integration examples for AI/ML workloads, alongside interfacing methods using analog front-end sensor systems.
Whether you’re exploring first-time SoC development or planning a low-risk hardware research project, this session will help clarify your path to design, implementation, and tape-out.
Key Takeaways
- The full SoC development lifecycle — concept to fabrication
- How nanoSoC enables IP re-use for faster prototyping
- Using silicon-proven Cadence workflows through CMC
- Integrating accelerators for AI/ML & sensor analog front-ends
- How to simplify tape-out for research and early-stage hardware platforms
Who Should Attend?
- SoC architects and chip designers
- Researchers and graduate students in microelectronics
- Hardware accelerator & AI/ML developers
- Anyone exploring experimental SoC design
About the Host Organizations
SoC Labs
A global academic community supporting SoC development within the Arm ecosystem — enabling reusable, community-driven hardware design across more than 120 universities.
CMC Microsystems
Accelerating research and innovation through shared platforms, expertise, and access to advanced design, manufacturing, and test technologies in Canada and beyond.
Presenter and Host
John Darlington — Lead, SoC Labs
John Darlington is part of Electronics and Computer Science at the University of Southampton, where he has collaborated with Arm for over 18 years. He leads the global SoC Labs community, connecting a network of 120+ universities working with reusable Arm-based hardware design.
John develops reference SoC architectures and works closely with industry to advance semiconductor fabrication capability in the UK.
Daniel Newbrook — Senior ASIC Design Engineer
Daniel Newbrook is a Senior ASIC Design Engineer at the University of Southampton, collaborating with SoC Labs and Arm. His work focuses on reusable SoC architectures designed for hardware accelerator integration.
Daniel specializes in low-power ASIC implementations and supports research teams in developing modular SoC solutions for cost-efficient silicon prototyping.
Ready to accelerate your next SoC project?
Register now and learn how SoC Labs and CMC can help simplify your path from concept to silicon.