Semiconductor Upskilling Training Program.
Professional IC Design Training for Canadian Engineers.
Structured, expert-led training for engineers at every stage — from new hires getting industry-ready to experienced professionals upskilling. Fully virtual. 8 weeks. Hands-on design projects with cloud CAD access.
Launching September 2026
FULLY VIRTUAL
Recorded sessions with live weekly Q&A
DESIGN TOOLS
Cloud-hosted tools — no local install required
8 WEEKS
Sept 1 – Oct 27, 2026
NO COMMITMENT
Free to register interest — registration opens June 2026
SEMICONDUCTOR INDUSTRY VALIDATED
Industry Training Advisory Group — Canadian IC design industry
WHO SHOULD ATTEND?
Built for Canadian IC engineers
- New hires and early-career engineers (0–3 years) in Canadian semiconductor companies
- Final-year MSc/PhD students seeking job readiness in IC design
- Industry professionals with prior IC design experience seeking advanced training, upskilling
Courses
The following course descriptions align with open job postings in the semiconductor ecosystem and have been ranked by Canadian industry. Use the form below to let us know which courses we should prioritize.
RTL, Synthesis and Verification
Hands-on RTL design, simulation, and synthesis using professional EDA tools. Participants run a complete RTL-to-netlist flow, interpret synthesis reports, and contribute to design review and simulation-based verification tasks.
Participants will learn
Write, simulate, and synthesize RTL designs using professional EDA tools (Cadence / Synopsys). Run an RTL-to-netlist flow, interpret synthesis reports, and contribute to RTL review and simulation-based verification. Ready to contribute at the block level within an RTL design team under senior engineer guidance.
Digital IC Design
Digital IC implementation steps covering floorplanning, clock tree synthesis, place-and-route, timing closure, and signoff using industry-standard tool flows.
Participants will learn
The entire implementation flow of Digital ICs. Organizing the floorplan, placing macros, positioning the IOs, generating power structures, placing physical and standard cells, clock tree synthesis, signal routing, interpreting timing reports and optimizing the design, equivalence checks and physical verification. Ready to contribute to digital design team day-to-day work under guidance.
High-Speed SerDes Design
Transistor-level SERDES transceiver design for data rates above 200 Gbps — covering TX/RX circuits, equalizers (FFE, CTLE, DFE), clock generation and recovery, and optical transceivers.
Participants will learn
Comprehensive transistor-level understanding of SERDES transceiver architecture. Graduates gain the technical depth to contribute to a high-speed IO design team, rounding their profile toward the SerDes domain.
Design Verification
Functional verification methodology for RTL designs — structured testbench development, constrained-random testing, and simulation-based sign-off flows.
Participants will learn
Analog and Mixed-Signal IC Design
Practical training in analog and mixed-signal IC design covering CMOS op-amps, Sigma-Delta converters, PLLs, and bandgap reference circuits using Cadence. Two structured projects from specification to simulation, building skills in CMOS layout and mixed-signal design.
Participants will learn
Design, analyze, and optimize analog circuits from specification to simulation. Complete two structured design projects covering op-amp topologies and switched-capacitor circuits, building skills in DC gain analysis, stability, frequency response, and noise characterization. Ready to contribute within a supervised analog IC design team.
FPGA Design & Implementation
End-to-end FPGA implementation covering synthesis, place-and-route, timing closure, and FPGA-specific architectural features using industry-standard tool flows.
Participants will learn
Implement, synthesize, and place-and-route a digital design on an FPGA target. Run timing closure, interpret timing reports, and apply FPGA-specific features including DSP blocks, block RAM, and clock management resources. Ready to contribute to FPGA design team day-to-day work under guidance.
How the program works
Certificate of Completion
Issued by CMC Microsystems on successful completion of all modules, labs, and design reviews.
Cloud CAD Access
Tools hosted via CMC infrastructure. No local installation required — accessible from day one.
TA-Supported Labs
Dedicated teaching assistant per cohort. Weekly live sessions of 60–90 minutes throughout the 8 weeks.
Industry-Aligned
Developed with input from Canadian semiconductor employers and the ITAG advisory group.
STAY INFORMED
Register Your Interest
Tell us which training areas are relevant to you. We will notify you when registration opens in June 2026. No commitment required.