Built for IC Engineers
- New hires and early-career IC engineers (0–3 years) at Canadian semiconductor companies
- Final-year MSc/PhD students seeking IC design job readiness
- Industry professionals seeking structured high-speed interface and mixed-signal design upskilling
Course Overview
This advanced course introduces the architecture and circuit design principles behind high-speed serial interfaces used in modern data communication systems. Participants will explore transmitter and receiver building blocks, equalization techniques, clock recovery concepts, and signal integrity considerations relevant to multi-gigabit serial links operating above 200 Gbps.
Developed with input from Canadian semiconductor employers and the Industry Training Advisory Group (ITAG).
Prerequisites
- Prior analog IC design exposure (required)
- Transistor-level circuit fundamentals (required)
- Frequency response & signal integrity (recommended)
What You Will Learn
- Understand the architecture of high-speed serial communication links
- Analyze TX and RX building blocks at the transistor level
- Apply equalization and signal conditioning techniques (FFE, CTLE, DFE)
- Interpret key SerDes performance trade-offs: power, performance, and area
- Participate in high-speed interface design discussions and architectural reviews
- Build foundational knowledge for SerDes-focused engineering roles
Topics Covered
- SerDes system architecture and link fundamentals
- Transmitter and receiver front-end design concepts
- Equalization techniques: FFE, CTLE, and DFE
- Clock generation and clock/data recovery (CDR)
- Channel impairments: loss, ISI, and eye-diagram interpretation
- Signal integrity considerations for multi-gigabit links
- Power, performance, and area trade-offs in high-speed I/O
- Design review and architecture evaluation methodologies
By the End of the Online Course, You’ll Be Able To:
- Describe the architecture of high-speed serial links and explain the role of TX/RX building blocks
- Apply equalization techniques (FFE, CTLE, DFE) and evaluate their trade-offs
- Interpret eye diagrams and assess signal integrity for multi-gigabit channels
- Analyze power, performance, and area trade-offs in SerDes circuit design
- Participate in SerDes architectural reviews and high-speed interface specification discussions
Equipment Requirements
- Windows, macOS, or Linux laptop
- Stable high-speed internet connection
- Modern web browser: Chrome, Edge, Firefox, or Safari
- VPN / SSH / Remote Desktop / VNC access, if required
- 8 GB RAM minimum, 16 GB recommended
- Power adapter for full-day training
