This 1.5-day training will cover the following topics:
- Schematic design creation and analysis of electro-optical circuits (PICs),
- Generation of layout implementation from source/schematic, or vice-versa,
- Layout-vs-schematic parameter and optical connectivity verification
- Introduction to photonic device compact modelling methodology in Verilog-A with recent Spectre™ circuit simulator enhancements.
Material will be divided into two sessions, where day one will cover Rapid Adoption Kit demonstrations and slide presentations, followed by hands-on, document-guided, self-learning software sessions with an instructor-led Q&A session.
Cadence Tools and License
Attendees will receive two-day access to Cadence tools and a Rapid Adoption Kit (RAK) for hands-on exercises and homework. This access will be provided through the CMC Compute Cloud. Participants can connect to and launch these tools from any computer with a stable internet connection. Detailed instructions on how to access and utilize these tools will be shared with all registered attendees.
Target Audience
- This training is open to all Engineers or researchers in the field of photonic integrated circuits, including Silicon photonics, thin film lithium Niobate, InP and others.
- Microelectronics engineers who would like to learn how they could work more collaboratively with photonics engineers.
- Other Engineers, interested in learning Cadence Virtuoso for various other applications, including Quantum and embedded systems
Pre-Requisites
No prerequisite is required for this training.
Schedule
| Date | Time | Location |
| December 2, 2025 | 9:00 am to 5:00 pm (EST) | Online |
| December 3, 2025 | 1:00 pm to 5:00 pm (EST) |
Speakers
| Name | Title |
| Momchil Meliv (Instructor) | Sr Principal Application Engineer at Cadence Design Systems |
| Ahmed Abumazwed | Staff Scientist, Photonics at CMC Microsystems |