This 1.5-day training will cover the following topics:
- Schematic design creation and analysis of electro-optical circuits (PICs),
- Generation of layout implementation from source/schematic, or vice-versa,
- Layout-vs-schematic parameter and optical connectivity verification
- Introduction to photonic device compact modelling methodology in Verilog-A with recent Spectre™ circuit simulator enhancements.
Material will be divided into two sessions, where day one will cover Rapid Adoption Kit demonstrations and slide presentations, followed by hands-on, document-guided, self-learning software sessions with an instructor-led Q&A session.
Cadence Tools and License
Attendees will receive two-day access to Cadence tools and a Rapid Adoption Kit (RAK) for hands-on exercises and homework. This access will be provided through the CMC Compute Cloud. Participants can connect to and launch these tools from any computer with a stable internet connection. Detailed instructions on how to access and utilize these tools will be shared with all registered attendees.
Target Audience
- This training is open to all Engineers or researchers in the field of photonic integrated circuits, including Silicon photonics, thin film lithium Niobate, InP and others.
- Microelectronics engineers who would like to learn how they could work more collaboratively with photonics engineers.
- Other Engineers, interested in learning Cadence Virtuoso for various other applications, including Quantum and embedded systems
Pre-Requisites
No prerequisite is required for this training.
Schedule
| Date | Time | Location |
| December 2, 2025 | 9:00 am to 5:00 pm (EST) | Online |
| December 3, 2025 | 1:00 pm to 5:00 pm (EST) |
Agenda
Day 1
Morning session: Basics of Analog Flow: A Design-Oriented Approach (Rapid Adoption Kit)
- Module 1: Starting with a project with Virtuoso
- Initial Setup of Virtuoso
- Creating a New Library and Cell
- Module 2: Schematic Design
- Schematic Creation Using Virtuoso Schematic Editor
- Symbol Creation
- Module 3: Schematic Testbench (for simulation analysis)
- Testbench Creation
- Modifying DUT Parameters
- Module 4: Pre-Layout Simulation
- Simulation Setup Using ADE Explorer and Assembler
- Waveform Results Analysis
- Generating Expressions
- Design Tuning Using Parameters
- Back annotation of Tuned Parameters
- Module 1: System Simulation: RF Widget Co-Simulation
- Co-Simulation (introduction)
- Simulation with SpectreX
- Demo Setup-Creation of maestro view
- Full System Simulation
- Module 2: (Photonics) Cascaded Waveguide Model: mode Properties (modeProp)
- ModeProp using SKILL
- ModeProp of a straight waveguide
- ModeProp of circular arc waveguide bend
- ModeProp on curved waveguides
- Module 3: (photonic) Schematic simulation (of back-annotated layout) using Spectre
- Back-Annotation of layout physical parameters
- 5.2.2 Simulation
Day 2
Four-hour open-hours session for Q&A and work on Day 1 unfinished labs/activities
Q&A
- What specific skills or prior knowledge are recommended for this training?
- No prior knowledge of Cadence Virtuoso design and analysis environment is required; the class is for new Virtuoso users.
- Will there be any additional resources or materials provided for self-study before or after the training?
- Yes, materials will be provided 1 week prior to the webinar. Self-study options are available through ASK Portal (Cadence Online Support), provided the user has a valid registration to the portal through their Academic Program or is licensed.
- Will this be interactive throughout the sessions or conducted as a separate session at the end?
- Day 1 sessions will be live and interactive as much as possible (minimizing the disruption of the material delivery).
- Day 2 session will be fully interactive, where students can catch up, finish Day 1 labs or ask questions.
Speakers
| Name | Title |
| Momchil Meliv (Instructor) | Sr Principal Application Engineer at Cadence Design Systems |
| Ahmed Abumazwed | Staff Scientist, Photonics at CMC Microsystems |