Semiconductor Upskilling Training Program

Semiconductor Upskilling Training Program

Generously supported by

High-Speed SerDes Design

Advanced transistor-level training in serial interface design: TX/RX circuits, equalization (FFE, CTLE, DFE), clock recovery, and signal integrity for >200 Gbps links.

Built for IC Engineers

  • New hires and early-career IC engineers (0–3 years) at Canadian semiconductor companies
  • Final-year MSc/PhD students seeking IC design job readiness
  • Industry professionals seeking structured high-speed interface and mixed-signal design upskilling

Course Overview

This advanced course introduces the architecture and circuit design principles behind high-speed serial interfaces used in modern data communication systems. Participants will explore transmitter and receiver building blocks, equalization techniques, and signal integrity considerations relevant to multi-gigabit serial links operating above 200 Gbps.

Developed with input from Canadian semiconductor employers and the Industry Training Advisory Group (ITAG).

Important Notes
  1. Training participants will have access to other proprietary and confidential information during the course; each participant is required to agree to the terms of the Access to Intellectual Property & Non-Disclosure Agreement at the time of registration.
  2. Cloud-hosted CAD/EDA tools provisioned by CMC Microsystems. No local installation required. Additional software license terms and conditions apply. 

Prerequisites

  • Prior analog IC design exposure (required)
  • Transistor-level circuit fundamentals (required)
  • Familiarity with Cadence tools for circuit simulation (required)
  • Frequency response & signal integrity (recommended)

What You Will Learn

  • Understand the architecture of high-speed serial communication links
  • Analyze TX and RX building blocks at the transistor level
  • Apply equalization and signal conditioning techniques (FFE, CTLE, DFE)
  • Anaylze key SerDes performance trade-offs: power, data rate, channel loss, and circuit complexity
  • Build foundational knowledge for SerDes-focused engineering roles

Topics Covered

  • SerDes system architecture and link fundamentals
  • Transmitter and receiver front-end design concepts
  • Equalization techniques: FFE, CTLE, and DFE
  • Clock generation and clock/data recovery (CDR)
  • Channel impairments: loss, ISI, and eye-diagram interpretation
  • Signal integrity considerations for multi-gigabit links
  • Power, performance, and area trade-offs in high-speed I/O
  • Architecture trade-off discussions

Weekly Schedule

CourseLectureLab
High-Speed SerDes DesignThursday
13:00-15:00 EDT
Tuesday
14:00-15:00 EDT

 

Outcomes

  • Describe the architecture of high-speed serial links and explain the role of TX/RX building blocks
  • Apply equalization techniques (FFE, CTLE, DFE) and evaluate their trade-offs
  • Interpret eye diagrams and assess signal integrity for multi-gigabit channels
  • Understand power, data rate, channel loss, and circuit complexity trade-offs in SerDes circuit design

Equipment Requirements

  • Windows, macOS, or Linux laptop
  • Stable high-speed internet connection
  • Modern web browser: Chrome, Edge, Firefox, or Safari
  • VPN / SSH / Remote Desktop / VNC access, if required
  • 8 GB RAM minimum, 16 GB recommended
  • Power adapter for full-day training

Instructor

Glenn Cowan
Lead Instructor
Professor, Electrical and Computer Engineering, Concordia University

Glenn Cowan received the B.A.Sc. degree from the University of Waterloo, Canada and the M.S. and Ph.D. degrees from Columbia University, New York, NY, in 2001 and 2005, respectively. 

In 2005, he joined the Communications Technology Department at the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research activities included CMOS circuits for high-speed communications, design for manufacturability, and circuits for the measurement of process variability. In 2007, he joined the Department of Electrical and Computer Engineering at Concordia University in Montreal, QC, Canada, where he is a professor. At Columbia, Dr. Cowan was a 2003 recipient of Analog Device’s Outstanding Student Designer Award. He was the 2005 recipient of Columbia’s Eliahu I. Jury award for outstanding achievement by a graduate student in the areas of systems, communications, or signal processing. His current research activities include low-power mixed-signal circuits for biomedical applications and wireline communication, as well as mixed-signal computation.

Prof. Cowan brings more than 20 years of mixed-signal IC design experience for applications ranging from programmable analog VLSI computation, biomedical signal acquisition, wireline communication, and power electronics for industrial applications. His work in analog computation launched 21st century interest in VLSI analog computation. He has explored various burst-mode schemes for power reduction, equalizer-based optical receivers, high-speed inductorless designs, noise analysis and optimization and more recently, drivers for microring modulators and their thermal stabilization. His expertise in this field is captured in his recently published book, Mixed-Signal CMOS for Wireline Communication, published in 2024 by Cambridge University Press.

Anatoly Syutkin
Lab Instructor

Anatoly Syutkin received his BEng (2018) and MASc (2021) degrees from Concordia University, Montreal, Canada. He is presently a PhD student in Electrical and Computer Engineering under the supervision of Dr. Glenn Cowan.

His primary research topic is the design of scalable, efficient, and robust analog and digital integrated circuits for neuromorphic computing. His work combines system-level simulations of neural networks and transistor-level designs. His other research interests include circuits for high-speed communication, analog filter design, and oscillator-based computing. He has frequently been the teaching assistant and lab demonstrator for electronics and VLSI courses at Concordia University.

How the Program Works

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Fully Virtual
Fully virtual delivery with live expert lectures and CAD lab sessions with weekly Q&A.

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Cloud-hosted
Cloud-hosted CAD/EDA tools provisioned by CMC Microsystems. No local installation required.

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Industry-aligned
Industry-aligned curriculum developed with the Industry Training Advisory Group and Canadian IC employers.

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Certification
Certificate of completion issued by CMC Microsystems upon completion of all modules and labs, with a minimum attendance requirement of 75% for both lectures and labs.

Eligibility Requirement:

The Fall 2026 cohort is open to participants based in Canada. Eligibility will be confirmed before enrollment is finalized. If participants are unsure whether they qualify, they should contact CMC Microsystems before registering.

Course Summary

Duration
8 weeks, September – October 2026


Live delivery
8 lectures and 8 lab sessions, 2 hours each


Format
Fully virtual, with live instruction, lab support, and Q&A


CAD/EDA access
Cloud-hosted tools provided by CMC Microsystems, no local installation required


Lab recordings
Available for 3 months after the cohort


Certificate
Issued by CMC Microsystems upon completion of all modules and labs

Register Now

Register by July 24, 2026 and save $100. Use coupon code SAVE100 at checkout.

FABrIC Members (Join FABrIC)
$1,000 CAD
$3,000 CAD

Participant must be based in Canada to register.

Contact

If you have any questions about the program content, registration process, or your eligibility to participate, please contact skills@cmc.ca.

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