Built for IC Engineers
- New hires and early-career IC engineers (0–3 years) at Canadian semiconductor companies
- Final-year MSc/PhD students seeking IC design job readiness
- Industry professionals seeking structured front-end design upskilling
Course Overview
This course goes beyond fundamentals: participants design, implement, and formally verify a minimal RISC-V processor core using Cadence EDA tools — Xcelium for simulation, Genus for synthesis, and JasperGold for formal verification — and graduate with a professional GitHub portfolio package. Three commitments drive the program: you build something real, you leave with something tangible, and you know what Canadian semiconductor teams expect from a new hire.
Developed with input from Canadian semiconductor employers and the Industry Training Advisory Group (ITAG).
Important Notes
- Training participants will have access to other proprietary and confidential information during the course; each participant is required to agree to the terms of the Access to Intellectual Property & Non-Disclosure Agreement at the time of registration.
- Cloud-hosted CAD/EDA tools provisioned by CMC Microsystems. No local installation required. Additional software license terms and conditions apply.
Prerequisites
- Basic digital logic & computer architecture
- Introductory HDL familiarity (beneficial)
- No prior EDA experience required
What You Will Learn
- Design, implement, and verify a complete RISC-V processor core across 8 weeks
- Run an end-to-end RTL-to-netlist flow using Cadence Xcelium and Genus; read timing and area reports
- Build and debug SystemVerilog testbenches with functional coverage metrics
- Apply SVA assertions and introductory formal verification with Cadence JasperGold to validate processor control logic
- Graduate with a GitHub portfolio package: RTL, testbench, synthesis reports, and design review notes
Topics Covered
- Design flow & RTL methodology: build the RISC-V ALU
- Combinational & sequential RTL: decoder and register file
- Simulation & debug: directed testing of the datapath
- SystemVerilog testbench: structured verification with coverage
- Synthesis flow: RISC-V core RTL to netlist (Cadence Genus)
- Constraints & timing: closing timing on the processor core
- Lint, RTL quality & intro to formal verification (Cadence JasperGold)
- Capstone: integration, GitHub package & mock design review
Weekly Schedule
Course | Lecture | Lab |
RTL, Synthesis & Verification | Friday 13:00-15:00 EDT | Friday 18:00-19:00 EDT |
Outcomes
- Design and implement a synthesizable RISC-V processor in SystemVerilog
- Run an RTL-to-netlist synthesis flow with Cadence Genus and interpret timing and area reports on a real processor design
- Build and debug SystemVerilog testbenches with functional coverage and SVA assertions
- Apply introductory formal verification with Cadence JasperGold (SVA property checking) to verify processor control logic
- Deliver a professional GitHub handoff package: RTL, testbench, synthesis reports, and design review notes
Equipment Requirements
- Windows, macOS, or Linux laptop
- Stable high-speed internet connection
- Modern web browser: Chrome, Edge, Firefox, or Safari
- VPN / SSH / Remote Desktop / VNC access, if required
- 8 GB RAM minimum, 16 GB recommended
- Power adapter for full-day training
Instructor
Tarek Ould-Bachir
Associate Professor at Polytechnique Montreal
Lead Instructor
Tarek Ould-Bachir received his M.A.Sc. and Ph.D. degrees in Electrical Engineering from Polytechnique Montréal, Montréal, QC, Canada, in 2008 and 2013, respectively.
He is currently an Associate Professor in the Department of Computer and Software Engineering at Polytechnique Montréal, where he also serves as Graduate Programs Coordinator. His research focuses on designing programmable architectures for high-performance embedded systems, with applications in real-time simulation, FPGA-based acceleration, and high-speed packet processing.
He has made significant contributions to electromagnetic transient (EMT) simulation, power electronics modeling, and hardware-in-the-loop (HIL) platforms. His recent work also addresses the cybersecurity of transportation systems, including autonomous vehicles and avionics platforms, where real-time constraints and system resilience are critical. In parallel, he is exploring unconventional computing paradigms, such as stochastic computing and Ising machines, to tackle complex combinatorial optimization problems in hardware.
Dr. Ould-Bachir has authored or co-authored more than fifty peer-reviewed publications in leading journals and conferences. He is actively involved in the IEEE Industrial Electronics Society (IES), where he currently serves as Chair of the Technical Committee on Electronic Systems on Chip (ESoC) for the 2026–2027 term. He regularly contributes to the organization of international workshops and conferences related to FPGA systems, embedded architectures, and cyber-physical simulation technologies. He is a licensed member of the Ordre des ingénieurs du Québec (OIQ) and a member of the IEEE, the Association for Computing Machinery (ACM), and the Regroupement Stratégique en Microsystèmes du Québec (ReSMiQ), a provincial strategic cluster supporting innovation in microsystems.
He is also a member of the Multidisciplinary Institute for Cybersecurity and Cyber Resilience (IMC²), an initiative hosted at Polytechnique Montréal that brings together academic, industrial, and governmental partners to advance cybersecurity. Additionally, he serves as co-director of the Microelectronics and Microsystems Research Group (GRM), which specializes in the design and validation of high-performance and secure integrated systems.
Nicolas Deloumeau
Lab Instructor
Nicolas Deloumeau received his M.A.Sc. in Computer Engineering from Polytechnique Montréal in 2025. His master’s thesis focused on heterogeneous tracing in FPGA systems. He currently works as a researcher for the Government of Canada.
